1. Field of the Invention
The present invention relates to sigma-delta modulators, and in particular, to sigma-delta modulators in which the resolution of the feedback digital-to-analog converter (DAC) is less than the resolution of the analog-to-digital converter (ADC) used in the modulator loop.
2. Related Art
Sigma-delta analog-to-digital modulators are often used in a sigma-delta ADC or sigma-delta DAC for providing shaping (filtering) of quantization noise. As the order of the sigma-delta modulator increases, the quantization noise is pushed further away in the frequency band from the signal being converted. Accordingly, sigma-delta ADCs and DACs, as well as their associated modulators, have become widely used in high precision applications.
A key design issue is the choice between a single-bit or a multi-bit quantizer, and in the case of a multi-bit quantizer, the number of bits to be used. With a single bit, the quantizer is binary and interpolation between its two output levels provides a linear response. Accordingly, single-bit architectures are often used since they provide high resolution without requiring accurate analog circuit elements.
However, since the resolution of the sigma-delta modulator relies on the oversampling ratio and the order of the modulator, obtaining a high signal-to-noise ratio (SNR) with relatively large signal bandwidths is problematic since the stability of higher order modulators costs a gain factor in the noise transfer function (NTF) and matching is critical in designing basic circuit blocks for cascaded architectures at high SNRs, e.g., above 90 dB.
A single-bit modulator also has a number of design requirements. Since both signal and quantization noise contribute to the output swing of the integrators, a large quantization step causes a large swing in the output voltage of the operational amplifiers. This requires using a small reference voltage relative to the power supply voltage.
A multi-bit quantizer increases the SNR (i.e., an improvement of SNR of approximately 6 dB for each additional bit). Also, using a multi-bit modulator reduces limits of a single-bit implementation, such as constraints on the reference voltage or demanding slew rate specifications, but does not provide the important characteristic of intrinsic linearity. Since the linearity of the noise-shaping elements depend upon the linearity of the DAC, it is necessary to use well-matched components to provide a DAC with the required linearity. Normally, such matching of integrated components is not adequate for high resolutions (e.g., more than 10-12 bits). Further, with a multi-bit architecture, the input of the downstream digital filter is a high-speed, multi-bit signal that requires complex processing prior to the first decimation. Further still, a multi-bit DAC is more difficult to fabricate in a very large scale integration (VLSI) environment with sufficient linearity needed for the high resolution quantized signal y1 and low resolution (truncated) signal y2.
Referring to FIG. 1, reducing the number of levels, or bits, in the internal DAC of a sigma-delta modulator has been implemented in the form of post-processing of the quantized y1 and truncated y2 signals. In this implementation, represented by its linear model, a classic second order sigma-delta modulator 10 includes adder circuits 12a, 12b, integrators 14a, 14b, a high resolution (i.e., multi-bit) a quantizer 16 (with quantization error εQ), a truncation circuit 18 (with truncation error εT), and a feedback DAC 20. A post-processor 22 processes the quantized y1 and truncated y2 signals.
The truncation of the quantized signal y1 adds truncation error εT and provides a lower resolution output signal y2. These signals y1, y2 can be expressed as follows:y1=p+εQ  (1)y2=p+εQ+εT=p+εQT  (2)
The truncated signal y2 is fed back to the adders 12a, 12b. Accordingly, this signal can be expressed as follows (where STF is the signal transfer function and NTF is the noise transfer function):y2=x*STF+εQT*NTF  (3)
The analog input signal p to the quantizer 16 can be expressed as follows:p=y1−εQ=y2−εQT  (4)
Substituting Equation (4) into Equation (3), the truncated signal y2 can be expressed as follows:y2=x*STF+(y2−y1+εQ)*NTF  (5)
Rearranging this produces the following expression:y2*(1−NTF)+y1*NTF=x*STF+εQ*NTF  (6)
Accordingly, it can be seen that signal processing is required to obtain shaping of the quantization error εQ instead of the larger truncation error εT. However, a problem associated with this technique is the post-processing 22 required must be done using a significantly larger number of bits due to the need to process both the quantized y1 and truncated y2 signals.
Other implementations have been proposed in which the digital feedback signal is truncated through a digital sigma-delta modulator that shapes the truncation error. However, since the resulting error is injected at the input of the modulator, its shaping must be of a higher order than the order of the analog modulator. Moreover, the number of bits at the output of the modulator (see, e.g., U.S. Pat. No. 6,980,144, the disclosure of which is incorporated herein by reference) correspond to the resolution of the quantizer, and the first stage of the digital filter used in the decimation is complex as it operates with a long input word. The order of sigma delta modulator used for the truncation must be higher than the order of the modulator as the corresponding error is injected at the input of the quantizer. Therefore, for a second order modulator the truncation must be done by at least a third order scheme with the additional request to have zero delay. This problem is limited by a cancellation of the effect of the truncation error in the analog domain (see, e.g., U.S. Pat. No. 6,967,608, the disclosure of which is incorporated herein by reference). Combining these techniques (e.g., as disclosed in U.S. Pat. Nos. 6,980,144 and 6,967,608) enables the use of a lower order in the truncation generator, although it must still be at least an order of two to ensure suitable shaping and accounting for mismatch between the analog and digital transfer functions used in the cancellation mechanism.